1. Technical Field
The present invention generally relates to a direct memory access (DMA) transmission, and more particularly to a timing mode selection apparatus for use in a DMA transmission system.
2. Related Art
In a direct memory access (DMA) transmission system, data is directly transmitted between a main memory and an input/output device without passing through a central processing unit. That is, while the central processing unit executes an input/output command, the data is directly transmitted to an associated device via the input/output device.
As explained in more detail below, it is typical for such a DMA transmission system to operate in the DMA mode, which includes a burst mode and a single mode. However, such a DMA transmission system can operate in only one mode at a time, either the burst mode or the single mode. Therefore, it is necessary at times to transfer between the burst mode and the single mode. However, it is not easy to freely change modes in view of the system conditions existing at the time. Therefore, there is a need for the development of a DMA transmission system having a mode selecting apparatus for handling both the burst mode and the single mode in such a system.
The following patents are considered to be representative of the prior art relative to the present invention, and are burdened by the disadvantage discussed above: U.S. Pat. No. 5,701,516 to Cheng et al., entitled High-Performance Non-Volatile RAM Protected Write Cahce Accelerator System Employing DMA And Data Transferring Scheme, U.S. Pat. No. 5,669,014 to Iyengar et al., entitled System And Method Having Processor With Selectable Burst Or No-Burst Write Back Mode Depending Upon Signal Indicating The System Is configured To Accept Bit Width Larger Than The Bus Width, U.S. Pat. No. 5,696,917 to Mills etal., entitled Method And Apparatus For Performing Burst Read Operations In An Asynchronous Nonvolatile Memory, U.S. Pat. No. 5,642,386 to Rocco Jr., entitled Data Sampling Circuit For A Burst Mode Communication System, U.S. Pat. No. 5,634,139 to Takita, entitled Microprocessor Using Feedback Memory Address To Internally Generate Bust Mode Transfer Period Signal For Controlling Burst Mode Data Transfer To External Memory, U.S. Pat. No. 5,634,099 to Andrews et al., entitled Direct Memory Access Unit For Transferring Data Between Processor Memories In Multiprocessing Systems, U.S. Pat. No. 5,613,162 to Kabenjian, entitled Method And Apparatus For Performing Efficient Direct Memory Access Data Transfers, U.S. Pat. No. 5,590,286 to Mehring et al., entitled Method And Apparatus For The Pipelining OfData During Direct Memory Accesses, U.S. Pat. No. 5,559,990 to Cheng et aL, entitled Memories With Burst Mode Access, U.S. Pat. No. 5,513,374 to Baji, entitled On-Chip Interface And DMA Controller With Interrupt Functions For Digital Signal Processor, U.S. Pat. No. 5,453,957 to Norris et al., entitled Memory Architecture For Burst Mode Access, U.S. Pat. No. 5,410,656 to King et al., entitled Work Station Interfacing Means Having Burst Mode Capability, U.S. Pat. No. 5,347,643 to Kondo et al., entitled Bus System For Coordinating Internal And External Direct Memory Access Controllers, U.S. Pat. No. 5,287,486 to Yamasaki etal., entitled DMA Controller Using A Programmable Timer, A Transfer Counter and An Or Logic Gate To Control Data Transfer Interrupts, U.S. Pat. No. 5,175,825 to Sarr, entitled High Speed, Flexible Source/Destination Data Burst Direct Memory Access Controller, U.S. Pat. No. 4,999,769 to Costers et al., entitled System With Plural Clocks For Bidirectional Information Exchange Between DMA Controller And I/O Devices Via DMA Bus, U.S. Pat. No. 4,799,199 to Scales III et al., entitled Bus Master Having Burst Transfer Mode, U.S. Pat. No. 4,530,053 to Kriz et al., entitled DMA Multimode Transfer Controls, U.S. Pat. No. 4,403,282 to Holberger et al., entitled Data Processing System Using A High Speed Data Channel For Providing Direct Memory Access For Block Data Transfers, and U.S. Pat. No. 4,084,154 to Panigrahi, entitled Charge Coupled Device Memory System With Burst Mode.